The International Business Machines (IBM) Personal Computers (PCs), and compatibles, have been widely popular largely because of their ability to expand functionality through an expansion bus. The first expansion bus, known as the Industry Standard Architecture (ISA) bus, operates at a maximum bus speed of 8.33 MHz and has a 16-bit data bus.
As computers became more powerful, the ISA bus was identified as a major bottleneck. The bus was too slow to keep up with the advances of high-powered microprocessors. Additionally, the width of the ISA bus was narrower than that supported by the microprocessor, thus further slowing down data transfers between the microprocessor and the bus peripherals. So alternative solutions were sought after.
One such solution was the Extended Industry Standard Architecture (EISA) bus. The EISA bus provided a 32-bit data path, burst data transfers and high speed DMA transfers. Since the EISA bus was actually an extension of the ISA bus, backward compatibility with the ISA bus was maintained.
A competing solution, known as the Micro-Channel Architecture (MCA), was offered by IBM. It also featured a 32-bit data path, burst data transfers and high speed DMA transfers. However, the IBM solution did not maintain backward compatibility with older ISA boards.
As the microprocessors evolved and grew more powerful, graphical operating systems, such as Microsoft Windows, OS/2 and UNIX also grew in popularity. The graphics required by the operating systems placed great demands on the video graphics hardware. The speed at which data could be transferred from main memory to graphics memory was a primary concern. To address this concern, many computer manufacturers began to place the graphics subsystem directly on the microprocessor bus. Thus, a de facto bus had evolved based on the microprocessor bus interface. Eventually, the bus became known as the VL-Bus. To a great extent, this solved the speed problem, but created another. Because manufacturers of video graphics boards, network interface boards, memory boards, etc., all wanted the greatest performance, they all desired a direct connection to the microprocessor. But as the load increased on the microprocessor outputs, system reliability was placed in jeopardy. Additionally, the VL-bus was inherently tied to a certain microprocessor interface. So the VL-bus only provided a limited solution.
Recognizing this concern, a mezzanine bus was adopted by the computer industry. This bus, known as the Peripheral Component Interconnect (PCI) bus, was designed to provide a supplemental, high speed, microprocessor independent bus. The bus was not intended to replace the general purpose ISA, EISA or microchannel expansion buses. The PCI bus is defined in the Peripheral Component Interconnect Specification, versions 1.0 and 2.0, available from the PCI Special Interest Group in care of Intel Corp. which are herein incorporated by reference. Currently the PCI bus operates with a 32-bit or optional 64-bit data bus at a 33 MHz clock speed. In the specification, basic signals and transactions are defined so that all devices conforming to the PCI bus will be able to communicate with one another.
One such device not conforming fully to PCI standards is the AMD 79C970 Ethernet controller. The 79C970 is a single chip network controller which suffers from non-conforming address timing. When the device is a bus master, the clock to address valid timing of the device does not allow enough time for propagation delay and address setup before the next clock edge. Thus, a device receiving an address from the 79C970 may not latch the proper address. As the 79C970 provides a highly integrated, high performance network controller subsystem, it is desirable to use the device without redesigning the 79C970 or the PCI bus.